1. Field of the Invention
The present invention relates to a method of manufacturing a capacitor and, more particularly, to a method of manufacturing a capacitor capable of simplifying the manufacturing process and increasing a capacitance of the capacitor.
2. Description of the Related Art
Recently, with the widespread use of computers, there has been an increase in demand for semiconductor devices. From a functional aspect, a semiconductor device is required to be operated at a high speed with a large storing capacitance. Accordingly, semiconductor technology is being developed to improve the level or degree of integration, the reliability and the response speed of semiconductor devices.
A DRAM device is widely used as a semiconductor memory device since it has a high capacitance with an ability of freely inputting and outputting information. The DRAM device generally consists of a memory cell area, which stores information in the form of an electric charge and a periphery circuit area for inputting/outputting data. A unit cell of the DRAM device generally includes one transistor and one storage capacitor.
In order to increase the level or degree of integration of the capacitor, the size of the capacitor has to be reduced. In addition, the capacitor is required to have a high storage capacitance to improve the performance of the semiconductor device. Accordingly, capacitor manufacturing process technology is being developed to try to meet the above requirements.
The structure of the capacitor has evolved from a planar capacitor to a stacked capacitor or a trench type capacitor. In the stacked capacitor, a cylindrical capacitor or a fin type capacitor is used so as to enlarge the surface area of a storage electrode.
FIGS. 1A to 1F are sectional views illustrating the manufacturing process of a cylindrical capacitor of a conventional semiconductor device.
Referring to FIG. 1A, a first insulating layer 12 is formed on a semiconductor substrate 10. Then, a photolithography process is carried out with respect to a predetermined portion of the first insulating layer 12 so that an electrode area of the semiconductor 10 is exposed, thereby forming a first hole 14.
Referring to FIG. 1B, a first conductive layer 16 is formed by depositing a conductive material such that the first hole 14 is filled up with the conductive material. Poly-silicon doped with impurities is used as the conductive material to be deposited.
Referring to FIG. 1C, an etch back process is carried out with respect to the first conductive layer 16. Accordingly, the poly-silicon at the top surface of the hole 14 is exposed and the poly-silicon filling in the first hole 14 remains so as to form a contact plug 16a. 
Referring to FIG. 1D, an etching stop layer 18 and a second insulating layer 20 are sequentially formed over the contact plug 16a. Then, a predetermined portion of the second insulating layer 20 is etched by performing a photolithography process, so that a second hole 22 exposing the contact plug 16a and a portion of the first insulating layer 12 peripheral to the contact plug 16a are formed. That is, the area of the bottom of the second hole 22 is larger than the area of the top of the contact plug 16a so that the area of the second hole 22 includes the contact plug area 16a and an area of the top surface of the first insulating layer 12 peripheral to the contact plug area 16a. 
Referring to FIG. 1E, a second conductive layer 24 is formed on upper portions of the exposed first insulating layer 12 and the contact plug 16a, and on sidewalls of the second hole 22 and upper surface of the second insulating layer 20. Then, the second conductive layer 24 is subject to an etch back process so as to expose the second insulating layer 20 outside of the second hole 22, thereby forming a storage electrode. The etch back process is carried out by a dry etching process or a chemical mechanical polishing (CMP) process.
Referring to FIG. 1F, a dielectric layer 26 and a plate electrode 28 are sequentially formed on the storage electrode so as to form a capacitor.
According to the conventional process as described above, the capacitor has a cylindrical storage electrode, so the storage capacitance can be increased. However, the increase of the storage capacitance is limited. In addition, the photolithography process and the polishing process have to be carried out several times in order to fabricate the capacitor. Therefore, the process time is increased thereby reducing the output of the capacitor manufacturing process.
The present invention is directed to solve the processing complexities of the prior art and to improve the capacitance value of a capacitor suitable for use in a DRAM cell. It is a feature of an embodiment of the present invention to provide a method of manufacturing a capacitor capable of simplifying the manufacturing process and increasing a capacitance value of the capacitor.
In a feature of an embodiment of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device in which a first insulating layer, an etching stop layer, and a second insulating layer are sequentially deposited on a semiconductor substrate. A predetermined portion of the second insulating layer is etched so as to form a preliminary hole for exposing the etching stop layer. A first hole is formed by transversely expanding the preliminary hole. A second hole is formed by etching a predetermined portion of the etching stop layer and the first insulating layer at a lower side of the first hole. The second hole exposes a part of an electrode area of the semiconductor substrate. The etched area of the second hole is narrower than the etched area of the first hole. A first conductive layer pattern is deposited uniformly on the sidewalls of the first and second holes and on the bottom surface of the second hole. A dielectric layer and a second conductive layer pattern are sequentially deposited on the first conductive layer pattern, to thereby complete the capacitor of a semiconductor device. The steps of forming the first and the second holes comprise the substeps of: providing a photoresist pattern for forming the preliminary hole on the second insulating layer; anisotropically etching the second insulating layer by using the photoresist pattern as an etching mask thereby forming the preliminary hole for exposing the etching stop layer; isotropically etching a sidewall of the preliminary hole in the second insulating layer, thereby forming the first hole which is transversely expanded; and anisotropically etching a predetermined portion of the exposed etching stop layer and then the first insulating layer at the lower side of the first hole by using the photo-resist pattern as the mask, thereby forming the second hole for exposing the semiconductor substrate. In the present invention, an hole in the photo-resist pattern for the first hole is formed on a portion of the second insulating layer in an area that corresponds to an upper center portion of the electrode area of the semiconductor substrate. The step of forming the first conductive layer pattern comprises the substeps of: depositing a first conductive layer on the sidewalls of the first and second holes, on the bottom surface of the second hole, and on the second insulating layer; and etching back the first conductive layer until the second insulating layer outside the first and second hole is exposed.
Since the first conductive layer pattern is deposited on the sidewall and the bottom surface of the second hole without filling in the second hole, the surface area of the storage electrode is enlarged so that the storage capacitance of the capacitor is increased. In addition, since the manufacturing process is simplified, the throughput of the capacitor is increased.
In another feature of an embodiment of the present invention, the second insulating layer is removed by a selective etching process after forming the first conductive layer pattern, thereby exposing both sides of the first conductive layer pattern above the etching stop layer, which helps to increase the capacitor area. A dielectric layer and a second conductive layer pattern are formed on the first conductive layer pattern resulting in a capacitor having a large capacitance value.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.